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STP40NF10 N-channel 100V - 0.025 - 50A TO-220 Low gate charge STripFETTM II Power MOSFET General features Type STP40NF10 VDSS 100V RDS(on) <0.028 ID 50A Exceptional dv/dt capability Low gate charge at 100C Application oriented characterization 100% avalanche tested 1 3 2 TO-220 Description This MOSFET is the latest development of STMicroelectronics unique "Single Feature SizeTM" strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. Internal schematic diagram Applications Switching application Order codes Part number STP40NF10 Marking P40NF10 Package TO-220 Packaging Tube January 2007 Rev 3 1/12 www.st.com 12 Contents STP40NF10 Contents 1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 4 5 Test circuit ................................................ 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/12 STP40NF10 Electrical ratings 1 Electrical ratings Table 1. Symbol VDS VGS ID (1) Absolute maximum ratings Parameter Drain-source voltage (vgs = 0) Gate- source voltage Drain current (continuous) at TC = 25C Drain current (continuous) at TC = 100C Drain current (pulsed) Total dissipation at TC = 25C Derating factor Value 100 20 50 35 200 150 1 27 385 - 55 to 175 Max. operating junction temperature Unit V V A A A W W/C V/ns mj C ID IDM (2) PTOT dv/dt(3) EAS (4) Peak diode recovery voltage slope Single pulse avalanche energy Storage temperature Tstg Tj 1. Limited by wire bonding 2. Pulse width limited by safe operating area 3. ISD 50A, di/dt 600A/s, VDD V(BR)DSS, Tj TJMAX. 4. Starting Tj= 25C, ID= 50A, VDD=25V Table 2. Rthj-a Tl Thermal data 1 62.5 300 C/W C/W C Thermal resistance junction-ambient Max Maximum lead temperature for soldering purpose Rthj-case Thermal resistance junction-case Max 3/12 Electrical characteristics STP40NF10 2 Electrical characteristics (TCASE=25C unless otherwise specified) Table 3. Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) On/off states Parameter Drain-source Breakdown voltage Zero gate voltage Drain current (VGS = 0) Gate-body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250 A, VGS = 0 VDS = Max rating VDS=Max rating,TC=125C VGS = 20V VDS = VGS, ID = 250A VGS = 10V, ID = 25A 2 3 0.025 Min. 100 1 10 100 4 0.028 Typ. Max. Unit V A A nA V Table 4. Symbol gfs (1) Ciss Coss Crss Qg Qgs Qgd Dynamic Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge VDS = 25V, f = 1 MHz, VGS = 0 Test conditions VDS = 15V, ID=28A Min. Typ. 22 2180 298 83.7 VDD = 80V, ID = 50A, VGS = 10V (see Figure 14) 57.6 13.3 17.5 76 Max. Unit S pF pF pF nC nC nC 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5. Table 5. Symbol td(on) tr td(off) tf Switching times Parameter Turn-on delay time Rise time Turn-off-delay time Fall time Test conditions VDD = 50V, ID = 25A RG = 4.7 VGS = 10V (see Figure 13) VDD = 27V, ID = 40A, RG = 4.7, VGS = 10V (see Figure 13) Min. Typ. 21 46 54 13 Max. Unit ns ns ns ns 4/12 STP40NF10 Table 6. Symbol ISD ISDM VSD (1) (2) Electrical characteristics Source drain diode Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 50A, VGS = 0 ISD = 50A, VDD = 25V di/dt = 100A/s, Tj = 150C (see Figure 15) 80 250 6.4 Test conditions Min. Typ. Max 80 320 1.5 Unit A A V ns nC A trr Qrr IRRM 1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 s, duty cycle 1.5% 5/12 Electrical characteristics STP40NF10 2.1 Figure 1. Electrical characteristics (curves) Safe operating area Figure 2. Thermal impedance Figure 3. Output characteristics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance 6/12 STP40NF10 Figure 7. Gate charge vs. gate-source voltage Figure 8. Electrical characteristics Capacitance variations Figure 9. Normalized gate threshold voltage vs. temperature Figure 10. Normalized on resistance vs. temperature Figure 11. Source-drain diode forward characteristics Figure 12. Normalized breakdown voltage vs. tj 7/12 Test circuit STP40NF10 3 Test circuit Figure 14. Gate charge test circuit Figure 13. Switching times test circuit for resistive load Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform 8/12 STP40NF10 Package mechanical data 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at : www.st.com 9/12 Package mechanical data STP40NF10 TO-220 MECHANICAL DATA DIM. A b b1 c D E e e1 F H1 J1 L L1 L20 L30 mm. MIN. 4.40 0.61 1.15 0.49 15.25 10 2.40 4.95 1.23 6.20 2.40 13 3.50 16.40 28.90 3.75 2.65 3.85 2.95 0.147 0.104 TYP MAX. 4.60 0.88 1.70 0.70 15.75 10.40 2.70 5.15 1.32 6.60 2.72 14 3.93 MIN. 0.173 0.024 0.045 0.019 0.60 0.393 0.094 0.194 0.048 0.244 0.094 0.511 0.137 0.645 1.137 0.151 0.116 inch TYP. MAX. 0.181 0.034 0.066 0.027 0.620 0.409 0.106 0.202 0.052 0.256 0.107 0.551 0.154 oP Q 10/12 STP40NF10 Revision history 5 Revision history Table 7. Date 16-Dec-2004 17-Aug-2006 31-Jan-2007 Revision history Revision 1 2 3 First version. The document has been reformatted. Typo mistake on Table 1. Changes 11/12 STP40NF10 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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